1. Field of the Invention
This invention relates to digital timing circuits and, more particularly, to timing circuits utilizing a variable rate driving signal to obtain variable time periods.
2. Description of the Prior Art
Digital transmission systems are well-known in which telephone voice subscriber signals are converted to pulse code modulated form for multiplexed transmission over a digital transmission facility. One such system is disclosed in the copending application of S. J. Brolin, Ser. No. 57,333, filed July 13, 1979, issued as U.S. Pat. No. 4,271,509 on June 2, 1981.
In such a system, each of a plurality of subscriber voice signals is encoded into an eight-bit pulse code modulated (PCM) code and the code words from each of the plurality are assigned to sequential time-slots on the transmission facility. When such a system is utilized in the telephone subscriber loop plant (the connection between the local telephone office and the telephone subscriber), it is necessary to transmit a variety of supervisory signals on the transmission system in addition to the encoded voice signals. One system for transmitting such supervisory signals utilizes the least significant position of a PCM word every sixth frame of the multiplexed signal. Successive pairs of such bits can then be used to transmit a dual bit supervisory code representing the supervisory control information transmitted on the line, as shown in the above-noted Brolin application.
In a digital subscriber loop transmission system where supervisory signals are translated to digital pulse form, it is necessary to ensure against inadvertent duplication of a valid supervisory code by bits or other noise on the transmission medium. Such verification is generally accomplished by ensuring that the valid code persists for a predetermined period of time prior to recognizing the reception of a valid signaling code. The verification function can be best accomplished by the use of sequential circuits such as digital counting circuits responsive to the reception of valid codes and which counts clock pulses up to a preselected count. When a number of such supervisory codes must be timed, or if other functions associated with supervisory signaling must be timed, it becomes convenient to use a single sequential circuit (digital counter) to count the timing periods for all of these various different functions.
When using a digital counter to generate a plurality of different timing periods, the granularity of the counting process, i.e., the repetition rate of a clock signal being counted, becomes important. In order to accurately count short periods of time, it is desirable to provide a clock repetition rate sufficiently fast to accurately identify the shorter periods. On the other hand, long timing periods which do not necessarily require the same timing accuracy would suggest longer periods between the clock pulses being counted. The solution to this dilemma at the present time is the provision of two or more different counters operating at different clock frequencies to provide the different timing periods. This solution, however, requires additional circuitry, thus increasing the cost, size and complexity of the overall circuit and reducing its reliability.